I am very pleased to announce that the EMC Society has a new Distinguished Lecturer (DL)! Dr. Joungho Kim was recently selected by the EMC Society Board of Directors as the newest Distinguished Lecturer for the 2009-2010 term. Dr. Kim is ready and anxious to begin his travels to EMC Society Chapters to make presentations and meet EMC Society members.
Remember, you can go to www.emcs.org and select ‘Distinguished Lecturer’ for a list of the current DLs. The Distinguished Lecturer program was created to provide local chapters with resources for chapter meetings at no cost to the chapter. The EMC Society funds the travel for DLs to travel to local chapters around the world.
I am pleased and honored to introduce Dr. Joungho Kim.
Dr. Joungho Kim received the B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and Ph.D. degree in electrical engineering from the University of Michigan, Ann Arbor, in 1993. In 1994, he joined the Memory Division of Samsung Electronics, where he was engaged in Gbit-scale DRAM design.
In 1996, he moved to the Korea Advanced Institute of Science and Technology (KAIST). He is currently a Professor in the Electrical Engineering and Computer Science Department, and the group director of Convergence Device and System Group. Since joining KAIST, his research centers on EMC modeling, design, and measurement methodologies of 3D IC, System-in-Package (SiP), and multi-layer PCB. Especially, his major research topic is focused on chip-package co-design and simulation for signal integrity, power integrity, ground integrity, timing integrity, and radiated emission of 3D IC and SiP. He has successfully demonstrated low noise and high performance designs of numerous SiP’s for wireless communication applications such as ZigBee, T-DMB, NFC, and UWB. He was on a sabbatical leave during the academic year from 2001 to 2002 at Silicon Image, Inc. in Sunnyvale, California. He was responsible for low noise package designs for SATA, FC, HDMI, and Panel Link SerDes devices.
He has authored and co-authored over 280 technical papers published at refereed journals and conference proceedings in modeling, design, and measurement of 3D IC, SiP, and PCB. Also, he has given more than 130 invited talks and tutorials at academia and related industry conferences. He received the Outstanding Academic Achievement Faculty Award of KAIST in 2006 and the Best Faculty Research Award of KAIST in 2008. Dr. Joungho Kim
was the symposium chair of the IEEE EDAPS 2008 Symposium. Currently, he is an Associate Editor of the IEEE Transactions on Electromagnetic Compatibility.
His presentation topics will be:
- EMC Design of IC and Package
We are facing considerably increased concerns on EMC issues of high performance integrated circuits and automotive semiconductor devices. They emit significant amounts of high frequency electromagnetic radiated and conducted emissions and are susceptible to external electromagnetic noises, suffering degradation of system performance and reliability. In this talk, novel design and analysis methodologies will be introduced to provide optimal design approaches by combining IC and package hierarchical designs of equalizer and PDN impedance. In addition, measurement results of IC and package co-design will be shown including RF circuits such as LNA and PA, and analog circuits such as PLL, DLL, OpAmp, and ADC.
- Low Electromagnetic Noise Design of System-in-Package
In order to meet intensively growing needs of extremely small form-factor semiconductor system solutions with sufficiently low cost for high-density and multi-function mobile platforms, 3D SiP has become the most promising design approach. However, heavily populated integration of multiple chips in three dimensional stacking structures on a multi-layer substrate in the SiP, inevitably yields considerable problems of signal integrity and power integrity. In this talk, design and analysis approaches will be introduced with the considerations of the signal integrity, power integrity, and electromagnetic coupling at the high speed and low noise 3D SiP’s. In addition, we will introduce design and text examples including RFID, DMB, ZigBee, and UWB SiP’s.
- Power Integrity of IC and Package
Power supply noise by digital switching is becoming the major source of electromagnetic noise generation and coupling in semiconductor systems. It could be even more serious in 3D SiP and IC based on vertical TSV type interconnections for high-density and multi-function mobile multimedia, computing, and communication system platforms. In this presentation, new modeling, design, and analysis approaches will be introduced with the consideration of the power integrity. The unique methods are based on simultaneous and hierarchical chip-package co-design and modeling in order to offer cost effective design solutions. In particular, we will show novel design methods and test results including thin film capacitor and EBG structures to minimize the power supply noise generation and coupling. EMC