Title: On-Chip ESD Protection for Integrated
Circuits and IC Design Perspective
Author: Albert Z. H. Wang
Publisher: Kluwer Academic Publishers, 2002
IC designers, whether they like it or not, have the nuisance job
of finding the ESD protection solution for the IC chip. If there
is no ESD protection provided within the IC, nobody will buy the
chips and a company will loose the market to its competitors.
What makes life more complicated is that as IC technologies advance,
the customer demands IC ESD robustness. The complexity of on-chip
ESD protection thus increases dramatically, and is often difficult
This book discusses ESD protection circuit design problems from
the IC designers perspective. It discusses fundamental and
advanced materials needed by a circuit designer for designing
ESD protection circuits. Among the salient features of this book
are: a) testing models and standards adopted by the US Department
of Defense, EIA/JEDEC, ESD Association, Automotive Electronics
Council, IEC, etc., b) ESD failure analysis, protection devices,
and protection of subcircuits, c) whole-chip ESD protection and
ESD-to-circuit interactions, d) advanced low parasitic compact
ESD protection structures for RF and mixed-signal ICs, and
e) mixed-mode ESD simulation-design methodologies for design prediction
This book is composed of ten chapters and three appendices of
some 300 pages. Each chapter comes with an appropriate number
of references. The book is written from a circuit designers
perspective and focuses on circuit design issues. The author tries
to involve several real world design examples for teaching purposes.
The book starts with Chapter 1 with an introduction to ESD protection
fundamentals including the ESD origins, ESD test models and standards.
In Chapter 2, the book moves on to ESD models. ESD events relevant
to ICs are depicted by ESD models, such as a human body model
(HBM), a machine model (MM), a charged device model (CDM), transmission
line pulsing (TLP), and IEC, corresponding to their origins. These
ESD test standards are the basis for developing ESD testing systems
as well as for ESD protection simulation and design. The discharges
in these ESD models can be simplified to a second order RLC network
with different parametric values. Critical ESD discharge parameters
must conform to the ideal discharge waveforms defined by the various
ESD standards. The ESD robustness of IC parts is classified by
performing ESD zapping measurements using ESD testing systems
based upon different ESD test standards. These standards tell
you what the ESD discharge waveform should look like, but they
do not tell you how to produce it.
Chapter 3 presents ESD protection device solutions. Single device
ESD protection structures and their basic device physics are discussed
in this chapter. The principles in ESD protection are to generate
a low-impedance shunting channel to safely discharge large ESD
currents and to clamp pad voltage to a sufficient low level. Diodes
are the simplest, but they have complications. BJT is the basis
for most active ESD protection structures including MOS and SCR
types. NMOS is the most commonly used ESD protection structure
in CMOS IC design, though it also has its drawbacks. SCR is one
of the most efficient ESD protection structures, offering ESD
protection of up to 80 V/um width, which makes it an attractive
choice for ESD protection of RF and mixed signal ICs. However,
success in designing SCR ESD protection largely depends upon how
well one can control the latch-up.
Chapter 4 presents ESD protection circuit solutions. These ESD
protection sub-circuits are developed in the book to meet the
ever-increasing demands for greater ESD robustness as well as
new technology features and circuit specifications. Multiple-finger
and gate-coupled MOS structures are commonly used for input protection.
For output pads, self-protection using an output buffer transistor
is an alternative to the dedicated ESD protection structures.
Low-trigger SCR structures of various types become more attractive
as chip size, parasitic effect, and layout become greater concerns
in advanced applications, provided that latch-up can be controlled.
One is cautioned to consider the net benefits before resorting
to any complex ESD protection scheme. The penalties associated
with large sizes, increased parasitic effects, and layout problems
should never be underestimated.
Advanced ESD protection is discussed in Chapter 5. Modern mixed-signal
and RF ICs require wide-angle considerations in ESD protection
circuit design. The ESD-circuit interaction becomes an inevitable
and critical issue in chip-level ESD protection design. The ESD-to-circuit
influence must be considered in chip designs. Circuit malfunction
due to possible accidental triggering of ESD protection structures
caused by a super fast RF signal emerges as a real problem. ESD
protection design really requires a full chip protection. Basic
ESD protection concepts, such as creating conductive paths, low
impedance discharging and low voltage clamping are the basis for
whole-chip ESD protection design.
Chapter 6 addresses ESD failure analysis (FA). FA is important
in the sense that FA results help circuit designers to better
understand ESD protection failure mechanisms and to avoid making
similar design mistakes repeatedly. Typical ESD failure signatures,
such as silicon filament, metal interconnect burnout, contact
spiking, gate oxide rupture, etc., are discussed. Case examples
are given to show how FA techniques can be used in practical design
debugging. Latent ESD failure phenomena are discussed with examples.
Analytical ESD device failure modeling is presented as well.
Layout and technology influences on ESD protection circuit design
are discussed in Chapter 7. In terms of layout, two basic considerations
should be kept in mind when doing ESD protection circuit design,
i.e., to ensure uniform current distribution and to make an area
efficient layout. Practical ESD-enhancement layout techniques
include the use of smoothed geometries, set up of adequate critical
spacing, properly placed contacts and vias, as well as optimized
metal interconnect routing, and so on. The use of a bonding pad
oriented ESD protection is a very attractive solution to high-pin
count area-sensitive chips. In regarding technological impact,
every simple new process technique designed to boost transistor
operation should be evaluated against its influences, such as
lightly doped-drain and silicidation, which can degrade ESD robustness
dramatically. Technology scaling generally makes ESD protection
circuit design more difficult.
Modeling of ESD is covered in Chapter 8. This chapter provides
an in-depth discussion of ESD simulation-design methodologies.
ESD simulation can be used in practice to guide ESD protected
circuit design with the final goal of providing a design prediction
for ESD protection. Several ESD simulation methods are available
for ESD protection design including TCAD-based device level simulation
and ECAD-based circuit level simulation. The advantage of device
level simulation is that it deals directly with semiconductor
device physics equations that are essential to investigating ESD
protection operation. However, it does not cover the whole picture
at circuit level, which is critical to ESD protection operations.
On the other hand, circuit level simulation takes care of the
circuit level function nature of ESD protection operation and
can be readily handled by ordinary IC circuit designers. As long
as accurate device models for ESD type devices are available,
circuit level ESD simulation can be realized by using a regular
SPICE-type simulator. Accurate ESD device modeling work is still
under research. What makes accurate ESD device modeling difficult
are the unique features associated with ESD behaviors, such as
very high current operation, avalanche breakdowns, thermal-electro
coupling effect, etc. Recognizing the multiple level coupling
effects in ESD protection operation, the book presents a mixed-mode
ESD simulation design methodology for practical ESD protection
circuit design. Several practical examples are presented to demonstrate
the value of the mixed-mode ESD simulation-design methodology.
Chapter 9 addresses ESD circuit interactions. Strong ESD-circuit
interactions exist. On one hand, the core circuit may affect the
performance of ESD protection significantly, resulting in pre-mature
ESD failures due to parasitic internal discharging structures.
On the other hand, ESD protection structures have inevitable parasitic
effects that influence the functionality of the core circuit substantially,
including global clock signal integrity, almost all key circuit
specifications, and noise performance. Chapter 10 ends with concluding
remarks and a discussion of future work by the author. EMC